FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review


  • Abdulmajeed Adil Yazdeen Dept. Information Technology Management Duhok Polytechnic University Duhok, Iraq
  • Subhi R. M. Zeebaree IT Dept., Duhok Polytechnic University, Duhok, Iraq
  • Mohammed Mohammed Sadeeq Duhok Polytechnic University
  • Shakir Fattah Kak Dept. Information Technology, Duhok Polytechnic University, Akre-Duhok, Iraq
  • Omar M. Ahmed Dept. Information Technology, Duhok Polytechnic University, Duhok, Iraq
  • Rizgar R. Zebari Research and Development Center, Nawroz University, Duhok, Iraq




Cryptography, DES algorithm, AES algorithm FPGAs Implementations, VHDL.


In recent days, increasing numbers of Internet and wireless network users have helped accelerate the need for encryption mechanisms and devices to protect user data sharing across an unsecured network. Data security, integrity, and verification may be used due to these features. In internet traffic encryption, symmetrical block chips play an essential role. Data Encryption Standard (DES) and Advanced Encryption Standard (AES) ensure privacy encryption underlying data protection standards. The DES and the AES provide information security. DES and AES have the distinction of being introduced in both hardware and applications. DES and AES hardware implementation has many advantages, such as increased performance and improved safety. This paper provides an exhaustive study of the implementation by DES and AES of field programming gate arrays (FPGAs) using both DES and AES. Since FPGAs can be defined as just one mission, computers are superior to them.


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How to Cite

Adil Yazdeen, A. ., Zeebaree , S. R. M. ., Mohammed Sadeeq, M., Kak, S. F. ., Ahmed, O. M. ., & Zebari, R. R. (2021). FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review. Qubahan Academic Journal, 1(2), 8–16. https://doi.org/10.48161/qaj.v1n2a38




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