FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review
Keywords:Cryptography, DES algorithm, AES algorithm FPGAs Implementations, VHDL.
In recent days, increasing numbers of Internet and wireless network users have helped accelerate the need for encryption mechanisms and devices to protect user data sharing across an unsecured network. Data security, integrity, and verification may be used due to these features. In internet traffic encryption, symmetrical block chips play an essential role. Data Encryption Standard (DES) and Advanced Encryption Standard (AES) ensure privacy encryption underlying data protection standards. The DES and the AES provide information security. DES and AES have the distinction of being introduced in both hardware and applications. DES and AES hardware implementation has many advantages, such as increased performance and improved safety. This paper provides an exhaustive study of the implementation by DES and AES of field programming gate arrays (FPGAs) using both DES and AES. Since FPGAs can be defined as just one mission, computers are superior to them.
S. Zeebaree, S. Ameen, and M. Sadeeq, "Social Media Networks Security Threats, Risks and Recommendation: A Case Study in the Kurdistan Region," vol. 13, pp. 349-365, 07/04 2020.
[W. Stallings, Data and computer communications: Pearson Education India, 2007.
S. Zeebaree, R. R. Zebari, K. Jacksi, and D. A. Hasan, "Security Approaches For Integrated Enterprise Systems Performance: A Review," Int. J. Sci. Technol. Res, vol. 8, 2019.
J.-P. A. Yaacoub, O. Salman, H. N. Noura, N. Kaaniche, A. Chehab, and M. Malli, "Cyber-physical systems security: Limitations, issues and future trends," Microprocessors and Microsystems, vol. 77, p. 103201, 2020.
W. Diffie and S. Landau, Privacy on the line: The politics of wiretapping and encryption: The MIT Press, 2010.
A. A. Salih, S. R. Zeebaree, A. S. Abdulraheem, R. R. Zebari, M. A. Sadeeq, and O. M. Ahmed, "Evolution of Mobile Wireless Communication to 5G Revolution," Technology Reports of Kansai University, vol. 62, pp. 2139-2151, 2020.
O. F. Mohammad, M. S. M. Rahim, S. R. M. Zeebaree, and F. Y. Ahmed, "A survey and analysis of the image encryption methods," International Journal of Applied Engineering Research, vol. 12, pp. 13265-13280, 2017.
D. A. Zebari, H. Haron, S. R. Zeebaree, and D. Q. Zeebaree, "Multi-Level of DNA Encryption Technique Based on DNA Arithmetic and Biological Operations," in 2018 International Conference on Advanced Science and Engineering (ICOASE), 2018, pp. 312-317.
M. A. Hussain and R. Badar, "FPGA based implementation scenarios of TEA Block Cipher," in 2015 13th International Conference on Frontiers of Information Technology (FIT), 2015, pp. 283-286.
G. MahendraBabu and K. Sridhar, "FPGA based Hybrid Random Number Generators," in 2020 4th International Conference on Electronics, Communication, and Aerospace Technology (ICECA), 2020, pp. 404-406.
A. J. Abd El-Maksoud, A. A. Abd El-Kader, B. G. Hassan, N. G. Rihan, M. F. Tolba, L. A. Said, et al., "FPGA implementation of sound encryption system based on fractional-order chaotic systems," Microelectronics Journal, vol. 90, pp. 323-335, 2019.
Z. N. Rashid, S. R. Zebari, K. H. Sharif, and K. Jacksi, "Distributed cloud computing and distributed parallel computing: A review," in 2018 International Conference on Advanced Science and Engineering (ICOASE), 2018, pp. 167-172.
O. Alzakholi, H. Shukur, R. Zebari, S. Abas, and M. Sadeeq, "Comparison among cloud technologies and cloud performance," Journal of Applied Science and Technology Trends, vol. 1, pp. 40-47, 2020.
S. Zeebaree and H. M. Yasin, "Arduino based remote controlling for home: power saving, security and protection," International Journal of Scientific & Engineering Research, vol. 5, pp. 266-272, 2014.
H. Shukur, S. R. Zeebaree, A. J. Ahmed, R. R. Zebari, O. Ahmed, B. S. A. Tahir, et al., "A State of Art Survey for Concurrent Computation and Clustering of Parallel Computing for Distributed Systems," Journal of Applied Science and Technology Trends, vol. 1, pp. 148-154, 2020.
S. R. Zebari and N. O. Yaseen, "Effects of Parallel Processing Implementation on Balanced Load-Division Depending on Distributed Memory Systems," J. Univ. Anbar Pure Sci, vol. 5, pp. 50-56, 2011.
S. Zeebaree, L. M. Haji, I. Rashid, R. R. Zebari, O. M. Ahmed, K. Jacksi, et al., "Multicomputer Multicore System Influence on Maximum Multi-Processes Execution Time," TEST Engineering & Management, vol. 83, pp. 14921-14931, 2020.
Z. N. Rashid, K. H. Sharif, and S. Zeebaree, "Client/Servers Clustering Effects on CPU Execution-Time, CPU Usage and CPU Idle Depending on Activities of Parallel-Processing-Technique Operations," Int. J. Sci. Technol. Res, vol. 7, pp. 106-111, 2018.
Z. Ageed, M. R. Mahmood, M. Sadeeq, M. B. Abdulrazzaq, and H. Dino, "Cloud computing resources impacts on heavy-load parallel processing approaches," IOSR Journal of Computer Engineering (IOSR-JCE), vol. 22, pp. 30-41, 2020.
K. H. Sharif, S. R. Zeebaree, L. M. Haji, and R. R. Zebari, "Performance Measurement of Processes and Threads Controlling, Tracking and Monitoring Based on Shared-Memory Parallel Processing Approach," in 2020 3rd International Conference on Engineering Technology and its Applications (IICETA), 2020, pp. 62-67.
Z. N. Rashid, S. R. Zeebaree, and A. Sengur, "Novel Remote Parallel Processing Code-Breaker System via Cloud Computing."
Z. S. Ageed, R. K. Ibrahim, and M. A. Sadeeq, "Unified Ontology Implementation of Cloud Computing for Distributed Systems," Current Journal of Applied Science and Technology, pp. 82-97, 2020.
W. M. Abduallah and S. R. M. Zeebaree, "New Data hiding method based on DNA and Vigenere Autokey," Academic Journal of Nawroz University, vol. 6, pp. 83-88, 2017.
H. M. Yasin, S. R. Zeebaree, and I. M. Zebari, "Arduino Based Automatic Irrigation System: Monitoring and SMS Controlling," in 2019 4th Scientific International Conference Najaf (SICN), 2019, pp. 109-114.
D. Zebari, H. Haron, and S. Zeebaree, "Security issues in DNA based on data Hiding: A review," International Journal of Applied Engineering Research, vol. 12, pp. 0973-4562, 2017.
N. Nayak, A. Chandak, N. Shah, and B. Karthikeyan, "Encryption and decryption using FPGA," in IOP Conference Series: Materials Science and Engineering, 2017, p. 052030.
B. O'Sullivan, Mercurial: The Definitive Guide: The Definitive Guide: " O'Reilly Media, Inc.", 2009.
R. Gupta, S. Tanwar, S. Tyagi, and N. Kumar, "Machine learning models for secure data analytics: A taxonomy and threat model," Computer Communications, vol. 153, pp. 406-440, 2020.
R. Bhanot and R. Hans, "A review and comparative analysis of various encryption algorithms," International Journal of Security and Its Applications, vol. 9, pp. 289-306, 2015.
K. Lata, "An Approach Towards Resisting Side-Channel Attacks for Secured Testing of Advanced Encryption Algorithm (AES) Cryptochip," in 2020 Third ISEA Conference on Security and Privacy (ISEA-ISAP), pp. 155-161.
P. Srivastava, E. Chung, and S. Ozana, "Asynchronous Floating-Point Adders and Communication Protocols: A Survey," Electronics, vol. 9, p. 1687, 2020.
J. Pandey, A. Gurawa, H. Nehra, and A. Karmakar, "An efficient VLSI architecture for data encryption standard and its FPGA implementation," in 2016 International Conference on VLSI Systems, Architectures, Technology and Applications (VLSI-SATA), 2016, pp. 1-5.
S. Vaudenay, A classical introduction to cryptography: Applications for communications security: Springer Science & Business Media, 2006.
V. Lytvyn, I. Peleshchak, R. Peleshchak, and V. Vysotska, "Information encryption based on the synthesis of a neural network and AES algorithm," in 2019 3rd International Conference on Advanced Information and Communications Technologies (AICT), 2019, pp. 447-450.
A. A. El-Moursy, A. M. Darya, A. S. Elwakil, A. Jha, and S. Majzoub, "Chaotic Clock Driven Cryptographic Chip: Towards a DPA Resistant AES Processor," IEEE Transactions on Emerging Topics in Computing, 2020.
P. R. L. C. R. Check, "20VL004-FPGA Based System Design."
C. Maxfield, The design warrior's guide to FPGAs: devices, tools and flows: Elsevier, 2004.
H. Shinba and M. Watanabe, "Radiation-hardened configuration context realization for field programmable gate arrays," Applied Optics, vol. 59, pp. 5680-5686, 2020.
J. Lambert, S. Lee, J. S. Vetter, and A. Malony, "In-depth optimization with the OpenACC-to-FPGA framework on an Arria 10 FPGA," in 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2020, pp. 460-470.
V. Ivanov and E. Nosov, "Serial communication protocol for FPGA-based systems," in Journal of Physics: Conference Series, 2019, p. 012044.
S. Setty, "Spartan: Efficient and general-purpose zkSNARKs without trusted setup," in Annual International Cryptology Conference, 2020, pp. 704-737.
A. Ilyas, M. R. Khan, and M. Ayyub, "FPGA based real-time implementation of fuzzy logic controller for maximum power point tracking of solar photovoltaic system," Optik, vol. 213, p. 164668, 2020.
D. Suratwala and G. Rahate, "A Comparative VHDL Implementation of Advanced Encryption Standard Algorithm on FPGA," in Machine Learning for Predictive Analysis, ed: Springer, 2021, pp. 343-351.
F. M. Nascimento, F. M. dos Santos, and E. D. Moreno, "A VHDL implementation of the Lightweight Cryptographic Algorithm HIGHT," algorithms, vol. 2, p. 5, 2015.
B. J. LaMeres, Introduction to logic circuits & logic design with VHDL: Springer, 2019.
S. R. Zeebaree, A. B. Sallow, B. K. Hussan, and S. M. Ali, "Design and simulation of high-speed parallel/sequential simplified DES code breaking based on FPGA," in 2019 International Conference on Advanced Science and Engineering (ICOASE), 2019, pp. 76-81.
K. Kumar, K. Ramkumar, and A. Kaur, "A Design Implementation and Comparative Analysis of Advanced Encryption Standard (AES) Algorithm on FPGA," in 2020 8th International Conference on Reliability, Infocom Technologies and Optimization (Trends and Future Directions)(ICRITO), 2020, pp. 182-185.
P. Sikka, A. R. Asati, and C. Shekhar, "Speed optimal FPGA implementation of the encryption algorithms for telecom applications," Microprocessors and Microsystems, vol. 79, p. 103324, 2020.
H. Zodpe and A. Sapkal, "An efficient AES implementation using FPGA with enhanced security features," Journal of King Saud University-Engineering Sciences, vol. 32, pp. 115-122, 2020.
S. R. Zeebaree, "DES encryption and decryption algorithm implementation based on FPGA," Indones. J. Electr. Eng. Comput. Sci, vol. 18, pp. 774-781, 2020.
E. A. Hagras and M. Saber, "Low power and high-speed FPGA implementation for 4D memristor chaotic system for image encryption," Multimedia Tools and Applications, vol. 79, pp. 23203-23222, 2020.
J. Zong, A. A. Hajomer, L. Zhang, W. Hu, and X. Yang, "Real-time secure optical OFDM transmission with chaotic data encryption," Optics Communications, vol. 473, p. 126005, 2020.
A. T. Hashim, A. M. Hasan, and H. M. Abbas, "Design and implementation of proposed 320 bit RC6-cascaded encryption/decryption cores on altera FPGA," International Journal of Electrical and Computer Engineering (IJECE), vol. 10, pp. 6370-6379, 2020.
F. S. Hasan and M. A. Saffo, "FPGA Hardware Co-Simulation of Image Encryption Using Stream Cipher Based on Chaotic Maps," Sensing and Imaging, vol. 21, pp. 1-22, 2020.
M. Madani and C. Tanougast, "FPGA implementation of an optimized A5/3 encryption algorithm," Microprocessors and Microsystems, vol. 78, p. 103212, 2020.
S. Madhavapandian and P. MaruthuPandi, "FPGA implementation of highly scalable AES algorithm using modified mix column with gate replacement technique for security application in TCP/IP," Microprocessors and Microsystems, vol. 73, p. 102972, 2020.
P. Visconti, S. Capoccia, E. Venere, R. Velázquez, and R. d. Fazio, "10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform," Electronics, vol. 9, p. 1665, 2020.
C.-H. Yang and Y.-S. Chien, "FPGA Implementation and Design of a Hybrid Chaos-AES Color Image Encryption Algorithm," Symmetry, vol. 12, p. 189, 2020.
B. M. Krishna, K. C. S. Kavya, P. S. Kumar, K. Karthik, and Y. S. Nagababu, "FPGA Implementation of Image Cryptology using Reversible Logic Gates," Int. J. of Advanced Trendsin Computer Science and Engineering, vol. 9, 2020.
X. Li, K. Wu, Q. Zhang, S. Lin, Y. Chen, and S. Y. Wong, "A High Throughput and Pipelined Implementation of the LUKS on FPGA," Journal of Circuits, Systems and Computers, vol. 29, p. 2050075, 2020.
A. Mhaouch, W. Elhamzi, and M. Atri, "Lightweight Hardware Architectures for the Piccolo Block Cipher in FPGA," in 2020 5th International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), 2020, pp. 1-4.
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Copyright (c) 2021 Abdulmajeed Adil Yazdeen, Subhi R. M. Zeebaree , Mohammed Mohammed Sadeeq, Shakir Fattah Kak, Omar M. Ahmed, Rizgar R. Zebari
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